VLSI implementation of a tree searched vector quantizer
| Title | VLSI implementation of a tree searched vector quantizer |
| Publication Type | Journal Articles |
| Year of Publication | 1993 |
| Authors | Kolagotla RK, Yu S-S, JaJa JF |
| Journal | Signal Processing, IEEE Transactions on |
| Volume | 41 |
| Issue | 2 |
| Pagination | 901 - 905 |
| Date Published | 1993/02// |
| ISBN Number | 1053-587X |
| Keywords | (mathematics);, 2, 20, chips;, coding;, compression;, data, design;, digital, image, implementation;, MHz;, micron;, PROCESSING, quantisation;, quantizer;, searched, signal, tree, TREES, vector, VLSI, VLSI; |
| Abstract | The VLSI design and implementation of a tree-searched vector quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical, and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using 2 mu;m N-well process on a 7.9 times;9.2 mm die. Each processor chip contains 25000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 20 MHz |
| DOI | 10.1109/78.193225 |